1. Field of the Invention
The present invention relates to a video signal processing apparatus for processing a video signal by using a memory thereof.
2. Related Background Art
FIG. 1 illustrates the schematic structure of a conventional video signal processing apparatus. Referring to FIG. 1, a video floppy disk 1 is rotated by a motor 1a at a predetermined speed of rotation so that a video signal recorded to the video floppy disk 1 is reproduced by a head 2 and it is then amplified by a pre-amplifier 3. Then, the frequency component of brightness signal Y and that of composite synchronization signal S are extracted by a high-pass filter (HPF) 4, while the frequency component of color difference line sequential signal B-Y/R-Y is extracted by a bandpass filter (BPF) 6. Signals denoting the extracted frequency components are respectively subjected to a variety of processes such as FM demodulation and de-emphasis processes in reproduction signal processing circuits 5 and 7 so that the signals are restored to the signal Y.multidot.S and the color difference line sequential signal B-Y/R-Y. Then, they are converted into digital signals by A/D converters 8 and 9, and then the digital signals are stored by a memory 19. The color difference line sequential signal B-Y/R-Y, which has been converted into the digital signal by the A/D converter 9, is delayed by a 1H delay line 10 by a degree of 1H (a horizontal period), and then it is stored by the memory 19.
A composite synchronization signal is separated from the signal Y.multidot.S which has been restored by the reproduction signal processing circuit 5, the composite synchronization signal being separated by a synchronization signal separation circuit 11. Furthermore, a vertical synchronization signal is separated from the composite synchronization signal by a vertical synchronization signal separation circuit 12. An H.multidot.V counter 13 for a memory counts the composite synchronization signals and the vertical synchronization signals and as well as controls an address control circuit 14 in accordance with the result of the counting operation. The address control circuit 14 controls operations of writing and reading data to and from the memory 19.
In accordance with the result of the counting operation performed by the H.multidot.V counter 13 for a memory, a decoder 15 generates composite synchronization signal C-SYNC, a burst flag BF denoting the period in which a burst signal is added and a variety of timing signals such as composite blanking signal C-BLNK which denotes a period in which no image is present in a retrace-line deletion period. The burst flag BF and the composite blanking signal C-BLNK are supplied to a video signal processing circuit 20, while the composite synchronization signal C-SYNC is supplied to an adder 24a.
A variety of data items read from the memory 19 are subjected to various processes such as the blanking process and the burst addition process in the video signal processing circuit 20. The signal Y processed by the video signal processing circuit 20 is converted into an analog signal by a D/A converter 22 before it is supplied to the adder 24a. On the other hand, the digital color difference signals B-Y and R-Y are subjected to an orthogonal two phase modulation process by a digital orthogonal two phase modulation circuit 21 so that they are modulated to digital chroma signals. Then, they are converted into analog signals by a D/A converter 23 before they are supplied to a buffer 26 and an adder 24b.
The adder 24a adds the signal Y supplied from the D/A converter 22 and the composite synchronization signal C-SYNC supplied from the decoder 15 to each other so as to transmit an addition signal (signal Y.multidot.S) to a buffer 25 and the adder 24b. The adder 24b adds the signal Y.multidot.S supplied from the adder 24a and the chroma signal supplied from the D/A converter 23 to each other so as to transmit a composite video signal via a buffer 27. The aforesaid operations are controlled by a system control unit 28a.
FIG. 2 illustrates the schematic structure of the conventional video signal processing apparatus. The apparatus shown in FIG. 2 is so arranged that a V-servo circuit 29 is additionally provided for the apparatus shown in FIG. 1 but the other structures are the same as those of the apparatus shown in FIG. 1. The apparatus shown in FIG. 2 is arranged in such a manner that the video floppy disk 1 is rotated in synchronization with the vertical synchronization signal V-SYNC transmitted from the decoder 15 at the time of the operation of reading data from the memory 19 by controlling the rotation of the motor 1a by the V-servo circuit 29. Then, a video signal recorded to another track of the video floppy disk 1 is reproduced, and the H.multidot.V counter 13 for a memory is reset at every 1H in synchronization with the horizontal synchronization signal, which has been, by a horizontal synchronization separation circuit 11a, separated from the Y.multidot.S signal of the video signal reproduced consecutively so that ensuing data is written to the memory 19. The above-mentioned operations are controlled by a system control unit 28b.
FIG. 3 illustrates the schematic structure of another conventional video signal processing apparatus. The apparatus shown in FIG. 3 is so arranged that an FIFO (First In First Out) memory 19a is used as the memory 19 of the apparatus shown in FIG. 1. Since the FIFO memory 19a is able to individually control the writing address and the reading address, the structure is so arranged that the operations of writing and reading data to and from the FIFO memory 19a are performed independently by controlling address control circuits 14a and 14b by an H.multidot.V counter 13a counting signals from synchronization separation circuits 11 and 12 for writing and an H.multidot.V counter 13b operating to count spontaneously signals from an internal source for reading which are provided respectively. The above-mentioned operations are controlled by a system control unit 28c.
However, since the video signal processing apparatus shown in FIG. 1 is so arranged that the H.multidot.V counter 13 for a memory is reset in response to the synchronization signal (refer to FIG. 4(b)) restored by the reproduction signal processing circuit 5 as shown in FIG. 4, a problem arises in that a discontinuous point (FIG. 4(a)) of the synchronization signal of the transmitted video signal is generated in a case where a new video data is written to the memory 19 consecutively to an operation of-reading data from the memory 19 and therefore the reproduced image becomes disordered in a case where the image is displayed on a monitor device on the like.
On the other hand, the conventional video signal processing apparatus shown in FIG. 2 is arranged in such a manner that the operation of reproducing the next track is started by rotating the video floppy disk 1 in synchronization with the vertical synchronization signal V-SYNC at the time of the operation of reading the data from the memory 19, and writing of next data to the memory 19 is performed. Therefore, writing and reading of data to and from the memory 19 can be performed consecutively. As a result, the above-mentioned problem can be overcome. However, it is difficult to completely continuously perform the data writing operation and the data reading operation to and from the memory 19 in each horizontal synchronization period. What is worse, it takes too long to start the data writing operation and the servo control must be always performed because the rotation servo control of the video floppy disk 1 must be performed prior to the writing operation. Furthermore, the necessity of supplying electricity to a drive apparatus for the video floppy disk 1 also at the time of the operation of reading data from the memory 19 causes the electric power consumption to become enlarged excessively.
Although the conventional video signal processing apparatus shown in FIG. 3 is able to maintain the continuity of the synchronization signals because the FIFO memory 19a is capable of independently controlling the data writing address and the reading address, the FIFO memory 19a costs excessively as compared with the general-purpose memory 19.